Processor-In-Memory System Simulator

The Problem: The extent of previous work on processor in memory systems using merged DRAM-logic process technology [1, 2, 3, 4] indicates that the technology has great promise. Most of the results to date, however, have been architectural studies with simulation results or proposed architectures. Relatively few designs make it to final silicon due to the prohibitively high Non-Recurring Engineering (NRE) costs of this new process technology. Of the designs that do make it to silicon, many have found that a merged DRAM-logic process is fickle: subtle noise or leakage problems can lead to a non-working DRAM array. This difficulty in realizing PIM architectures in silicon has left the research community with a lack of real platforms for compiler and application development, and thus there is much uncertainty about our ability to efficiently utilize these typically fine-grained parallel processor systems.